Integration of a semiconductor integrated circuit, especially an integrated circuit using MOS transistors is advancing. With this advancement of integration, miniaturization of the MOS transistor used in the circuit has proceeded to a nano level. Although a basic circuit of a digital circuit is an inverter circuit, when miniaturization of the MOS transistor constituting this inverter circuit advances, there occurs a problem that suppressing a leak current is difficult, reliability is reduced to a hot carrier effect, and an area share ratio of the circuit is hardly decreased because a necessary current amount must be assured. To solve such a problem, a surrounding gate transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer has been proposed, and a CMOS inverter circuit using the SGTs has been proposed (see, e.g., Japanese Patent Application Laid-open No. JP2-71556, Japanese Patent Application Laid-open No. JP2-188966, and Japanese Patent Application Laid-open No. JP3-145761).
FIG. 1 shows a conventional two-stage CMOS inverter using SGTs in which an output from a first inverter is input to a second inverter (S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Nobel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE JSSC, Vol. 30, No. 9, 1995). The first inverter includes two pMOS SGTs 01 and 02 and one nMOS SGT 03. The second inverter includes two pMOS SGTs 04 and 05 and two nMOS SGTs 06 and 07. The conventional two-stage CMOS inverter with the SGTs utilizes the SGTs in which each of a first power supply wiring line VSS and a second power supply wiring line VCC is supplied via a diffusion layer of a silicon substrate through contacts. That is, the power supply lines of the nMOS and the pMOS are arranged in one side of a lower portion of a gate region that is different from a region on the substrate where the NMOS and the pMOS are arranged. A resistance of the diffusion layer is extremely higher than that of a metal wiring line for power supply. When the resistances of the first power supply wiring line VSS and the second power supply wiring line VCC are increased, a source voltage applied to the NMOS SGT is increased beyond a first power supply voltage VSS and a source voltage applied to the pMOS SGT is reduced beyond a second power supply voltage VCC. When the source voltage for the nMOS SGT is increased beyond the first power supply voltage VSS, a driving current for the NMOS SGT is decreased. When the source voltage for the pMOS SGT is reduced beyond the second power supply voltage VCC, a driving current for the pMOS SGT is decreased. When the driving current for the transistor is decreased, a speed of charging/discharging a capacitance at an output terminal of the inverter is reduced. When the speed for charging/discharging the capacitance at the output terminal of the inverter is reduced, a delay time of the inverter is increased. Therefore, a metal wiring line is provided to the diffusion layer through many contacts, the first power supply voltage VSS is applied to a source of the NMOS SGT, and the second power supply voltage VCC is applied to a source of the pMOS SGT.
Further, the conventional SGT CMOS inverter forms contacts in the diffusion layer of a drain to be connected with a metal wiring line, thereby providing a first inverter output. The metal wiring line at the first inverter output is connected with a gate of polysilicon as a second inverter input through the contacts.
That is, in the conventional substrate grounded type two-stage CMOS inverter using the SGTs, a ratio of a contact area with respect to a circuit occupied area is large. Furthermore, when the resistances of the first power supply wiring line VSS and the second power supply wiring line VCC are increased, a delay time of the inverter is increased.